1. Field of Invention
The present invention relates in general to the electrical connector field. More particularly, the present invention relates to a method and apparatus for providing horizontally split vias in printed wiring boards (PWBs) and other substrates, such as interconnect substrates.
2. Background Art
Electrical connectors are in widespread use in the electronics industry. In many computer and other electronic circuit structures, an electronic module such as a central processor unit (CPU), memory module, application-specific integrated circuit (ASIC) or other integrated circuit, must be connected to a printed wiring board (PWB). Printed wiring boards are also known as printed circuit boards (PCBs). When populated with one or more electronic components, a printed wiring board is often referred to as a printed wiring board assembly (PWBA) or a printed circuit board assembly (PCBA). In connecting an electronic module to a PWB, individual electrical contacts on the base of the electronic module must be connected to a plurality of corresponding individual electrical contacts on the PWB. This set of contacts on the PWB dedicated to contacting the electronic module contacts is known as a land grid array (LGA) site when a LGA connector is used to connect the electronic module to the PWB.
Typically, the PWB contains a plurality of vias, each electrically connecting a conductive trace on one layer of the PWB to one or more conductive traces on one or more other layers of the PWB. The vias may be at the LGA site, for example, or elsewhere on the PWB. FIG. 1 illustrates exemplary types of conventional vias in a cross-section of a PWB 100 having a plurality of insulator layers 102 and conductive traces 104. Typically, vias are electroplated (e.g., copper or other highly conductive metal) onto through-holes drilled into the PWB. Such a via, which extends from one surface of the PWB to the other surface of the PWB, is referred to as a plated-through-hole (PTH) via. An exemplary PTH via 110 is illustrated in FIG. 1. In addition to or in lieu of PTH vias, it is also not uncommon for high layer-count PWBs to have blind vias, which are visible only on one surface of the PWB, and/or buried vias, which are visible on neither surface of the PWB. An exemplary blind via 120 is illustrated in FIG. 1, as well as an exemplary buried via 130. Blind vias and buried vias are advantageous over PTH vias in certain respects (e.g., blind vias and buried vias are more efficient from a space utilization perspective than PTH vias). However, blind vias and buried vias are significantly more expensive to fabricate than PTH vias because blind vias and buried vias are produced utilizing additional fabrication steps that are performed as the insulator layers of the PWB are fabricated.
Generally, it is advantageous to increase a substrate's wiring density. Although blind vias and buried vias are more efficient from a space utilization perspective than PTH vias, it is typically impractical to significantly increase a substrate's wiring density through the use of increased blind vias and buried vias.
It should therefore be apparent that a need exists for an enhanced mechanism for increasing wiring density in PWBs and other substrates, such as interconnect substrates.